Welcome to Shoufeng’s Webpage

About Me

"I must go, I must travel, I must enter freedom. "

Hi! Welcome to my personal website. This is Shoufeng Zhang (张寿峰 in Chinese). I am currently enrolled at the University of Hong Kong as an undergrad, started 2025 fall.

My academic interests lie at the intersection of computer architecture, digital system design, and machine learning systems. In recent years, I have explored areas such as RISC-V-based CPU design, FPGA system prototyping, low-bit quantized neural network accelerators, and hardware-aware machine learning optimization.

For my future exploration, I am particularly interested in AI/ML system co-design, including how emerging hardware can shape the next generation of ML algorithms, and how system-level optimization can unlock efficiency for real-world AI workloads. I am also curious about robot learning and embodied intelligence, bridging low-level system control with high-level decision-making. Fields like operating systems, compilers, and ML-specific hardware accelerators are also on my roadmap.

I am always open to conversations, collaboration opportunities, and creative projects — feel free to reach out if you share similar passions!

Education

• The University of Hong Kong — Bachelor of Engineering Elite Programme
  Expected May 2029

• Carnegie Mellon University — Summer Session Student (GPA: 4.0/4.0)
  Summer 2024

• Beijing 101 High School — International Baccalaureate Diploma Programme
  Jul. 2025

Achievements

• 2025 The University of Hong Kong Entrance Scholarship
• 2024 International Mathematical Modelling Challenge: Outstanding Award (Top 1%).
• 2023 Science Talent Program: Annual National Outstanding Student.
• 2023 USAMO Qualifier: Top scores from AMC12 and AIME.
• 2023 British Physics Olympiad (BPhO): Gold (Global Top 8%).
• Standardized Test Scores: TOEFL 117/120.

Selected Projects

• Hardware-Accelerated 1-Bit Quantization Using PyRTL for Efficient Neural Network Design
  Mentored by James Read (Georgia Tech). Designed a 1-bit MAC unit for a Systolic Array with PyRTL, reducing area requirements and critical path length.

• Yishengyizhen Program by Chinese Academy of Sciences
  In the ysyx program, I explored computer architecture and systems. Designed circuits with Verilog/Vivado for RV32 instructions and built a simplified RV32I emulator in C.

• A Comprehensive Analysis of AI Research Topics Using LDA and LDAvis: Insights from arXiv Data
  Mentored by Prof. Gangyi Ding. Applied LDA and LDAvis to analyze AI topics using arXiv data.

More

Outside of academics, I am passionate about photography. I am a contracted contributor at iStock by Getty Images and 500px China. Some of my works have been published on Visual China Group and 500px.